Prof.
Ahmad
Hiasat
academic
Biography:
Prof. Ahmad Hiasat got his B.Sc. and M.Sc. in Electrical Engineering from the University of Jordan. In 1995, he earned his PhD in Systems Engineering from Oakland University, MI, USA. He joined PSUT in 1996 and became a full Professor in 2005.
Seconded from PSUT, Prof. Hiasat was the Chairman and CEO of Jordan’s Telecommunications Regulatory Commission between 2006 and 2010, and Chairman and CEO of the Energy Regulatory Commission of Jordan from 2011 to 2012. His research interests include computer arithmetic, residue number system, digital median filters and VLSI design.
Academic Rank:
Professor
Faculty:
King Abdullah II School of Engineering
KAE Departments:
Computer Engineering
Phone:
5359949
Extension:
223
Fax:
5347295
Office:
EE 449
Email:
Curriculum Vitae:
Publications:
Selected Journal Papers
- A. Hiasat “An Efficient Reverse Converter for the Three-Moduli Set (2 n+1 -1; 2n; 2n - 1) ” IEEE Transactions on Circuits and Systems TCAS-II, vol. 64, no. 8, pp 962-966, August 2017.
- A. Hiasat, "A Efficient RNS Scalers for the Extended Three-Moduli Set (2n -1, 2n+p, 2n + 1)," IEEE Transactions on Computers, vol. 66, no. 7, pp 1253 - 1260, July 2017.
- A. Hiasat, "A Residue to Binary Converter for the Extended Four Moduli Set {2n-1; 2n + 1; 22n + 1; 22n+p}," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, No. 7, pp 2188 - 2192, July 2017.
- A. Hiasat “A Reverse Converter and Sign Detectors for an Extended RNS Five Moduli Set” IEEE Transactions on Circuits and Systems TCAS-I, vol. 64, No. 7, pp 111 – 121, January 2017.
- A. Hiasat, "A Sign Detector for a Group of Moduli," IEEE Transactions on Computers, vol.
65, no. 12, pp 3580 -3590 , Dec. 2016.
- N. Abu-Shikhah, A. Hiasat, W. Al-Rabadi, “A photovoltaic proposed generation promotion policy—The case of Jordan”, Energy Policy, vol. 49, No. 1, pp 154–163, October 2012.
- A. Hiasat,"VLSI Implementation of New Arithmetic Residue to Binary De-coders," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, No. 1, pp 153-158, January 2005.
- A. Hiasat, "A Suggestion for a New RNS-based Multiplier for a Family of Moduli," International Journal of Computers and their Applications, vol. 11, no. 2, pp. 92-97, June 2004.
- A. Hiasat and A. Sweidan, "Residue to Binary Decoder for an Enhanced Moduli Set," IET Proceedings: Computers and Digital Techniques, vol. 151, no. 2, March 2004.
- O. Hasan and O. Hasan, and A. Hiasat, "Limiter Discriminator Detection of Narrow-Band Doubinary FSK in a Land Mobile Channel," the International Journal of Communication Systems, vol. 17, no. 1, pp 85-97, February 2004.
- A. Hiasat, "A Suggestion for Fast Residue Multiplier for a Family of Moduli of the form (2n- (2p + 1))," The Computer Journal (The British Computer Society), Volume 47, Issue 1, pp. 93-102, January 2004.
- A. Hiasat, "Arithmetic binary to residue encoders for moduli (2n- (2p + 1))," IET Proceedings: Computers and Digital Techniques, vol. 150, no. 6, pp 369-374, November 2003.
- A. Hiasat and O. Hasan, "Bit-serial Architecture for Rank Order and Stack Filters," INTEGRATION, the VLSI Journal, Elsevier Science, Vol. 36, no. (1-2), pp 3-12, September 2003.
- A. Hiasat and A. Sweidan, "Residue Number System to Binary Converter for the Moduli Set (2n-1, 2n-1, 2n+1)," Journal of Systems Architecture, Elsevier Science, vol. 49, no. (1-2), pp. 53-58 August 2003.
- A. Hiasat, "New digital sweep oscillator structures," IET Proceedings: Circuits, Devices and Systems, vol. 150, no. 3, pp 179-184, June 2003.
- A. Hiasat, "Efficient residue to binary converter," IET Proceedings: Computers and Digital Techniques, Vol. 150, No. 1, pp 11-16, January 2003.
- A. Hiasat, "High-Speed and Reduced-Area Modular Adder Structures for RNS," IEEE Transactions on Computers, Vol. 51, No. 1, pp 84-89, January 2002.
- A. Sweidan and A. Hiasat, "On the theory of error control based on moduli with common factors," Journal of Reliable Computing, Kluwer Academic, vol. 7, issue 4, p 209-218, July 2001.
- A. Hiasat, "RNS Arithmetic Multiplier for Medium and Large Moduli,"IEEE Transactions on Circuits and Systems, Part II, pp 937-940, September 2000.
- A. Hiasat, "New efficient structure for a modular multiplier for RNS," IEEE Transactions on Computers, Vol. 49, No. 2, pp 170-174, February 2000.
- A. Hiasat, M. Al-Ibrahim and K. Garaibeh, "Design and implementation of a new median filtering algorithm," IET Proceedings: Vision, Image and signal Processing, vol. 146, no.5, pp 273-278, October 1999.
- A. Hiasat and A. Al-Khateeb, "New high-resolution digital sinusoidal oscillator structure with extremely low frequency and sensitivity," Int'l J. of Electronics, vol. 86, No. 3, , pp 287-296, March 1999.
- A. Hiasat and H. Zohdy, "Combinational logic approach for implementing An improved approximate squaring function" IEEE Journal of Solid State Circuits, vol. 34,no. 2, pp 236-240, February 1999.
- A. Hiasat and A. Al-Khateeb, "Efficient digital sweep oscillator with extremely low sweep rates," IET Proceedings: Circuits, Devices and Systems, vol. 145,no. 6, pp 409-414, December 1998.
- A. Hiasat and H. Zohdy, "Semi-Custom VLSI design and implementation of a new efficient RNS division algorithm," The Computer Journal, vol. 42, no. 3, pp 232-240, 1999.
- A. Hiasat, "New designs for a sign detector and a residue to binary converter, "IET Proceedings: Circuits, Devices and Systems, pp 477-482, August 1993.
- A. Hiasat, "New memoryless mod (2n+1) residue multiplier," IET Electronics Letters, vol. 28, no. 3, pp 314-315, January 1992.
- A. Sweidan and A. Hiasat, "New efficient memoryless residue to binary converter, " IEEE Transactions, CAS-35, pp 1441-1444, November 1988.
Refereed Conference Papers (here are a few)
- A. Hiasat, "Semi-custom VLSI chip implementation of a new two- dimensional separable median filtering algorithm,” the 8th IEEE International Conference on Electronics, Circuits and Systems, 2001. ICECS 2001, pp 841-844, Sep. 2-5, 2001.
- A. Hiasat, "VLSI design and implementation of a separable two-dimensional median filter," NORSIG 2000: IEEE NORDIC Signal Processing Symposium, Sweden, June 13-15, 2000.
- A. Hiasat, "Full-custom VLSI design of new high-speed modular adder structures", Proceedings of IEEE ICECS'99, pp 1221-1224, September 1999.
- A. Hiasat, “An Efficient Residue-Based Arithmetic Multiplier,” IMACS/GAMM International Symposium on Scientific Computing, Computer Arithmetic and Validated Numerics SCAN-98, pp 168-171, Budapest, Hungary, Sep. 22-25, 1998.
- A. Sweidan and A. Hiasat, “An RNS Error Correction Scheme Based on Moduli With Common Factors,” IMACS/GAMM International Symposium on Scientific Computing, Computer Arithmetic and Validated Numerics SCAN-98, pp 54-57, Budapest, Hungary, Sep. 22-25, 1998.
- H. Zohdy and A. Hiasat, "VLSI Design and Implementation of An Improved Squaring Circuit By Combinational Logic," INVITED paper, 31st Annual Asilomar Conference on Signals, Systems, and Computers, Proceedings, pp 426-429, Pacific Grove, CA, November, 1997.
- A. Hiasat and H. Zohdy, "Design and implementation of an RNS division algorithm," Proc. of the 13th IEEE Symposium on Computer Arithmetic, Asilomar, CA, pp 240-209, July 1997.
- H. Abdel-Aty-Zohdy and A. Hiasat, ``VLSI Design and Implementation of An Improved Squaring Circuit By Combinational Logic," INVITED paper, 31st Annual Asilomar Conference on Signals, Systems, and Computers, Proceedings, pp 426-429, Pacific Grove, CA, November, 1997.
- A. Hiasat, "Semi-custom VLSI design for RNS multipliers using combinational logic approach," Proceedings of the IEEE ICECS'96, pp 935-938, October 1996.
- A. Hiasat and H. Abdel-Aty-Zohdy, ``Combinational Logic Design Approach of A Residue-Arithmetic Multiplier," Proceedings of the IEEE 1996 Midwest Symposium on Circuits and Systems, MWSCAS96, Ames, Iowa, pp. 541- 543, August 1996.
- A. Hiasat, and H. Zohdy "Fast and customized RNS division algorithm", Proceedings of the IEEE ICECS'95, pp 20-23, December 1995.
- A. Hiasat and H. Zohdy, "An algorithm for the design of a residue to binary converter," in the Proceedings of 38th IEEE MidWest Symposium on Circuits and Systems, pp 1280-1283, August 1995.
- -A. Hiasat and H. Zohdy, "High-speed division algorithm for residue number system," Proceedings of the 1995 IEEE International Symposium on Circuits and Systems ISCAS'95, pp 1996-1999, May 1995.
- A. Hiasat and H. Zohdy, "Design and implementation of a fast and compact residue-based semi-custom VLSI arithmetic chip," Proc. of the 37th IEEE MidWest Symp. on Circuits and Systems, vol. 1, pp 428-431, August 1994.
- A. Hiasat, "A novel design for a multipurpose residue-to-mixed-radix decoder," Proc. of the 35th IEEE MidWest Symp. on Circuits and Systems, vol.1, pp 24-27, August 1992.